The present invention relates to a thin film transistor and a method of fabricating the same, and more particularly to a staggered thin film transistor with an improved ohmic contact structure between source/drain electrodes and an amorphous silicon layer and a method of forming an improved ohmic contact structure between source/drain electrodes and an amorphous silicon layer.
In recent years, requirement for reduction in the cost of manufacturing a thin film transistor color liquid crystal display has been on the increase. Reduction in the cost of fabricating thin film transistor arrays is the essential issue in order to realize the required reduction in the manufacturing cost of the thin film transistor color liquid crystal display. An inverse staggered thin film transistor with a bottom gate structure has widely been used. Notwithstanding, a forward staggered thin film transistor with a top gate structure would be advantageous in lower manufacturing cost. Particularly, a forward staggered thin film transistor with source/drain electrodes comprising transparent and conductive films would be attractive in reduced manufacturing cost because this transistor may be fabricated by reduced number of manufacturing processes.
A first conventional method of fabricating a first conventional forward staggered thin film transistor will be described with reference to FIGS. 1A through 1C wherein this first conventional forward staggered thin film transistor has an ohmic contact between source/drain electrodes and an amorphous silicon layer. This is disclosed in the Japanese laid-open patent publication No. 61-198678.
With reference to FIG. 1A, a glass substrate 1 is prepared. An indium tin oxide film 4 is deposited by a sputtering method on a top surface of the glass substrate 1. An n.sup.+ -doped amorphous silicon 10 is then deposited by a chemical vapor deposition method on a top surface of the indium tin oxide film 4.
With reference to FIG. 1B, laminations of the indium tin oxide film 4 and the n.sup.+ -doped amorphous silicon 10 are patterned by a photolithography method and dry etched to define source/drain electrodes 6 on the top surface of the glass substrate 1.
With reference to FIG. 1C, an amorphous silicon film 7 is deposited by a plasma chemical vapor deposition method over the source/drain electrodes 6 and the top surface of the glass substrate 1 A gate insulation film 8 made of silicon nitride is then deposited by a plasma chemical vapor deposition method on a top surface of the amorphous silicon film 7. A metal film 9 such as a chromium film is deposited by a sputtering method on a top surface of the gate insulation film 8. Laminations of the amorphous silicon film 7, the gate insulation film 8 and the metal film 9 are patterned by a photo-lithography method and a dry etching to define a gate electrode 9, the gate insulation film 8 and the amorphous silicon film 7. The n.sup.+ -doped amorphous silicon 10 is so heavily doped as to provide ohmic contacts between the indium tin oxide films 4 and the amorphous silicon film 7. As a result, the forward staggered amorphous silicon thin film transistor is completed.
A second conventional method of fabricating a second conventional forward staggered thin film transistor will be described with reference to FIGS. 2A through 2C wherein this second conventional forward staggered thin film transistor has an ohmic contact between source/drain electrodes and an amorphous silicon layer. The ohmic contact is formed by a treatment in an impurity containing plasma atmosphere. This is disclosed in the Japanese laid-open patent publication No. 62-81064.
With reference to FIG. 2A, a glass substrate 1 is prepared. An indium tin oxide film 4 is deposited by a sputtering method on a top surface of the glass substrate 1.
With reference to FIG. 2B, the indium tin oxide film 4 is patterned by a photo-lithography method and a dry etching to define source/drain electrodes 6 on the top surface of the glass substrate 1. Subsequently, surfaces of the glass substrate 1 and the source/drain electrodes 6 are subjected to a PH.sub.3 plasma 11 to introduce phosphorus into surface regions of the glass substrate 1 and the source/drain electrodes 6 whereby not only phospho-containing indium tin oxide films 4a are formed in the top and side surface regions of the source/drain electrodes 6 but also phospho-containing glass films 1a are formed in the top surface region of the glass substrate 1.
With reference to FIG. 2C, an amorphous silicon film 7 is deposited by a plasma chemical vapor deposition method over the phospho-containing indium tin oxide films 4a and the phospho-containing glass films 1a. A gate insulation film 8 made of silicon nitride is then deposited by a plasma chemical vapor deposition method on a top surface of the amorphous silicon film 7. A metal film 9 such as a chromium film is deposited by a sputtering method on a top surface of the gate insulation film 8. Laminations of the amorphous silicon film 7, the gate insulation film 8 and the metal film 9 are patterned by a photo-lithography method and a dry etching to define a gate electrode 9, the gate insulation film 8 and the amorphous silicon film 7. The phospho-containing indium tin oxide films 4a is so heavily doped as to provide ohmic contacts between the indium tin oxide films 4 and the amorphous silicon film 7. Also the phospho-containing glass films 1a is heavily doped. As a result, the forward staggered amorphous silicon thin film transistor is completed.
A third conventional method of fabricating a third conventional forward staggered thin film transistor will be described, wherein this third conventional forward staggered thin film transistor has an ohmic contact between source/drain electrodes and in amorphous silicon layer. The third conventional forward staggered thin film transistor also has a indium thin oxide film entirely doped with phosphorus. The phospho-containing indium thin oxide film may be deposited by sputtering a phospho-containing indium thin oxide target. Alternatively, the phospho-containing indium thin oxide film may be formed by a deposition of an indium thin oxide film and subsequent exposure of the indium thin oxide film to a PH.sub.3 plasma. Further alternatively, the pbospho-containing indium thin oxide film may be formed by a deposition of an indium thin oxide film and subsequent thermal diffusion of phosphorus into the indium thin oxide film. This is disclosed in the Japanese laid-open patent publication No. 62-81057.
The above first conventional method of the of fabricating the first conventional forward staggered thin film transistor has the following problems. As described above, the n.sup.+ -doped amorphous silicon film 10 is formed on the indium tin oxide film 4 and then the amorphous silicon film 7 is formed on the n.sup.+ -doped amorphous silicon film 10. The n.sup.+ -doped amorphous silicon film, however, has a deteriorated adhesiveness to other films, for which reason the n.sup.+ -doped amorphous silicon film 10 is likely to be peeled from the indium tin oxide film 4 or the amorphous silicon film 7 is likely to be peeled from the n.sup.+ -doped amorphous silicon film 10.
Further, the n.sup.+ -doped amorphous silicon film 10 is formed in the other deposition system than the deposition system used for forming the indium tin oxide film 4. This increases the number of the fabrication processes, resulting in the manufacturing cost being risen.
The above second conventional method of the of fabricating the second conventional forward staggered thin film transistor also has the following problems. As described above, not only the phospho-containing indium tin oxide films 4a are formed in the top and side surface regions of the source/drain electrodes 6 but also the phospho-containing glass films 1a are formed in the top surface region of the glass substrate 1. For those reason, when the amorphous silicon film 7 is then formed on the phospho-containing indium tin oxide films 4a and the phospho-containing glass films 1a, phosphorus may be diffused from the phospho-containing glass films 1a into the amorphous silicon film 7 whereby a phospho-diffused amorphous silicon region is formed in the amorphous silicon film 7. The indium tin oxide films 4 serving as the source/drain electrodes are connected to each other via the phospho-diffused amorphous silicon region. This may cause a current leakage between the indium tin oxide film source/drain electrodes 4 through the phospho-diffused amorphous silicon region of the amorphous silicon film 7. The current leakage deteriorates the performance of the forward staggered thin film transistor.
Further, the amorphous silicon film 7 is formed in the other deposition system than the deposition system used for forming the indium tin oxide film 4. This increases the number of the fabrication processes, resulting in the manufacturing cost being risen.
The above third conventional method of the of fabricating the third conventional forward staggered thin film transistor also has the following problems. As described above, an impurity is doped into the entire parts of the indium tin oxide film at a relatively high impurity concentration. For those reasons, the impurity doped indium tin oxide film has a high resistivity.
Further, if the phospho-containing indium thin oxide film is deposited by sputtering a phospho-containing indium thin oxide target which is expensive, then the manufacturing cost is increased.
If, alternatively, the phospho-containing indium thin oxide film is formed by a deposition of an indium thin oxide film and subsequent exposure of the indium thin oxide film to a PH.sub.3 plasma to introduce phosphorus into the entire parts of the indium thin oxide film, the PH.sub.3 plasma treatment is carried out in other system than the deposition system for depositing the indium thin oxide film. This increases the number of the fabrication processes, resulting in the manufacturing cost being risen.
If, further alternatively, the phospho-containing indium thin oxide film is formed by a deposition of an indium thin oxide film and subsequent thermal diffusion of phosphorus into the indium thin oxide film, the thermal diffusion of phosphorus is carried out in other system than the deposition system for depositing the indium thin oxide film. This increases the number of the fabrication processes, increasing in the manufacturing cost. Further, the glass; substrate is weak to the thermal treatment at a high temperature because of its softening point in the order of 500.degree. C., for which reason the glass substrate is unavailable practically.
In the above circumstances, it had been required to develop a novel forward staggered thin film transistor having source/drain electrodes with a reduced resistivity and has high performances but free of current leakage as well as develop a novel method of fabricating such forward staggered thin film transistor at a low manufacturing cost.